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programmable low power gyroscope adis16251 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2009 analog devices, inc. all rights reserved. features yaw rate gyroscope with digital range scaling 20/sec, 40/sec, and 80/sec settings 14-bit digital gyroscope sensor outputs 12-bit digital temperature sensor output calibrated sensitivity and bias in-system, auto-zero for bias drift calibration digitally controlled sample rate digitally controlled frequency response dual alarm settings with configurable operation embedded integration for short-term angle estimates digitally activated self-test digitally activated low power mode interrupt-driven wake-up spi-compatible serial interface 49 hz sensor bandwidth auxiliary 12-bit adc input and 12-bit dac output auxiliary digital input/output single-supply operation: 4.75 v to 5.25 v 2000 g powered shock survivability applications instrumentation control platform control and stabilization motion control and analysis avionics instrumentation navigation image stabilization robotics functional block diagram sclk din dout dio1 dio2 spi port temperature sensor self-test power management auxiliary i/o alarm digital control signal conditioning and conversion calibration and digital processing adis16251 vcc filt rate com a ux adc aux dac vref gyroscope sensor rst cs 0 6463-001 figure 1. general description the adis16251 is a complete angular rate, measurement sys- tem, available in a single compact package enabled by analog devices, inc. i sensor? integration. by enhancing analog devices i mems? sensor technology with an embedded signal processing solution, the adis16251 provides factory-calibrated and tunable digital sensor data in a convenient format that can be accessed using a simple spi serial interface. the spi interface provides access to measurements for the gyroscope, temperature, power supply, and one auxiliary analog input. easy access to calibrated digital sensor data provides developers with a system-ready device, reducing development time, cost, and program risk. the device range can be digitally selected from three different settings: 20/sec, 40/sec, and 80/sec. unique charac- teristics of the end system are accommodated easily through several built-in features, including a single-command auto-zero recalibration function, as well as a configurable sample rate and frequency response. additional features can be used to further reduce system complexity, including: ? configurable alarm function ? auxiliary 12-bit adc and dac ? two configurable digital i/o ports ? digital self-test function system power dissipation can be optimized via the adis16251 power management features, including an interrupt-driven wake-up. the adis16251 is available in an 11 mm 11 mm 5.5 mm, laminate-based, land grid array (lga) package with a temperature range of ?40c to +85c.
adis16251 rev. a | page 2 of 2 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 recommended layout ................................................................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 10 overview ...................................................................................... 10 relative angle estimate ............................................................. 10 factory calibration .................................................................... 10 auxiliary adc function ........................................................... 10 basic operation .............................................................................. 11 serial peripheral interface (spi) ............................................... 11 data output register access .................................................... 12 programming and control ............................................................ 13 control register overview ....................................................... 13 control register structure ........................................................ 13 calibration ................................................................................... 14 global commands ..................................................................... 14 operational control ................................................................... 15 status and diagnostics ............................................................... 17 second-level assembly ................................................................. 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 11/09rev. 0 to rev. a change to endurance parameter, table 1 ..................................... 4 4/07revision 0: initial version
adis16251 rev. a | page 3 of 3 specifications t a = ?40c to +85c, v cc = 5.0 v, angular rate = 0/sec, 1 g , 80/sec range setting, unless otherwise noted. table 1. parameter conditions min typ max unit sensitivity clockwise rotation is positive output at 25c, dynamic range = 80/sec 1 0.01832 /sec/lsb at 25c, dynamic range = 40/sec 0.00916 /sec/lsb at 25c, dynamic range = 20/sec 0.00458 /sec/lsb initial tolerance at 25c, dynamic range = 80/sec 0.2 1 % temperature coefficient see figure 8 325 ppm/c power supply variation at 25c, 1 , v cc = 4.75 v to 5.25 v 0.21 % nonlinearity best fit straight line 0.1 % of fs bias in run bias stability at 25c, 1 0.016 /sec turn-on-to-turn-on bias stability at 25c, 1 0.018 /sec angular random walk at 25c, 1 3.6 /hour temperature coefficient see figure 7 0.03 /sec/c linear acceleration effect any axis 0.2 /sec/ g power supply sensitivity at 25c, 1 , v cc = 4.75 v to 5.25 v 0.4 /sec/v noise performance output noise at 25c, 80/sec rang e, no filtering 0.48 /sec rms at 25c, 40/sec range, 4-tap filter setting 0.28 /sec rms at 25c, 20/sec range, 16-tap filter setting 0.14 /sec rms rate noise density at 25c, f = 25 hz, 80/sec range, no filtering 0.056 /sec/hz rms frequency response 3 db bandwidth see the analog bandwidth section for adjustment 49 hz sensor resonant frequency 14 khz self-test state change for positive stimulus 80/sec dynamic range setting 1672 2884 4449 lsb change for negative stimulus 80/sec dynamic range setting ?1672 ?2884 ?4449 lsb internal self-test cycle time 20 ms temperature sensor output at 25c 0 lsb scale factor 6.88 lsb/c adc input resolution 12 bits integral nonlinearity 2 lsb differential nonlinearity 1 lsb offset error 4 lsb gain error 2 lsb input range 0 2.5 v input capacitance during acquisition 20 pf on-chip voltage reference 2.5 v accuracy at 25c ?10 +10 mv temperature coefficient 40 ppm/c output impedance 70
adis16251 rev. a | page 4 of 4 parameter conditions min typ max unit dac output 5 k/100 pf to gnd resolution 12 bits relative accuracy for code 101 to code 4095 4 lsb differential nonlinearity 1 lsb offset error 5 mv gain error 0.5 % output range 0 to 2.5 v output impedance 2 output settling time 10 s logic inputs input high voltage, v inh 2.0 v input low voltage, v inl 0.8 v for cs signal when used to wake up from sleep mode 0.55 v logic 1 input current, i inh v ih = 3.3 v 0.2 10 a logic 0 input current, i inl v il = 0 v all except rst ?40 ?60 a rst 2 ?1 ma input capacitance, c in 10 pf digital outputs output high voltage, v oh i source = 1.6 ma 2.4 v output low voltage, v ol i sink = 1.6 ma 0.4 v sleep timer timeout period 3 0.5 128 sec start-up time initial 160 ms sleep mode recovery 2.5 ms flash memory endurance 4 10,000 cycles data retention 5 t j = 55c 20 years conversion rate minimum conversion time smpl_prd setting = 0x01 3.906 ms maximum conversion time smpl_prd setting = 0x0f 7.75 sec maximum throughput rate smpl_prd setting = 0x01 256 sps minimum throughput rate smpl_prd setting = 0x0f 0.129 sps power supply operating voltage range, v cc 4.75 5.0 5.25 v power supply current normal mode at 25c 18 ma fast mode at 25c 44 ma sleep mode at 25c 335 a 1 the sensor is capable of 150/sec, but the specifications herein are for 80/sec only. 2 the rst pin has an internal pull-up. 3 guaranteed by design. 4 endurance is qualified as per jedec standard 22 method a117 and measured at ?40c, +25c, +85c, and +125c. 5 retention lifetime equivalent at the junction temperature (t j ) of 55c, as per jedec standard 22 method a117. retention lifetime decreases with junction temperature.
adis16251 rev. a | page 5 of 5 timing specifications table 2. parameter description min 1 typ max 1 unit f sclk fast mode (smpl_prd 0x07; f s 64 hz) 0.01 2.5 mhz normal mode (smpl_prd < 0x07; f s 56.9 hz) 0.01 1.0 mhz t datarate data rate period, fast mode (smpl_prd 0x07; f s 64 hz) 32 s data rate period, normal mode (smpl_prd < 0x07; f s 56.9 hz) 42 s t datastall data stall time, fast mode (smpl_prd 0x07; f s 64 hz) 9 s data stall time, normal mode (smpl_prd < 0x07; f s 56.9 hz) 12 s t cshigh chip select high 1/f sclk t cs chip select to clock edge 48.8 ns t dav data output valid after sclk edge 2 100 ns t dsu data input setup time before sclk rising edge 24.4 ns t dhd data input hold time after sclk rising edge 48.8 ns t df data output fall time 5 12.5 ns min t dr data output rise time 5 12.5 ns min t sfs cs high after sclk edge 3 5 ns flash update time (power supply must be within range) 50 ms 1 guaranteed by design; typical specifications are not tested or guaranteed. 2 the msb presents an exception to this parameter. the msb clocks out on the falling edge of cs . the rest of the dout bits are clocked out after the falling edge of sclk and are governed by this specification. 3 this parameter may need to be expanded to allow for proper capture of the lsb. after cs goes high, the dout line goes into a high impedance state. cs sclk t datarate t datastall 06070-026 figure 2. spi chip select timing cs sclk dout din 1 2 3 4 5 6 15 16 a5 a4 a3 a2 d2 msb db14 d1 lsb db13 db12 db10 db11 db2 lsb db1 t cs t sfs t dav t dhd t dsu w/r * *not defined 06463-003 figure 3. spi timing (utilizing spi settings typically identified as phase = 1, polarity = 1)
adis16251 rev. a | page 6 of 6 absolute maximum ratings table 3. parameter rating acceleration (any axis, unpowered, 0.5 ms) 2000 g acceleration (any axis, powered, 0.5 ms) 2000 g v cc to com ?0.3 v to +6.0 v digital input/output voltage to com ?0.3 v to +5.5 v analog inputs to com ?0.3 v to +3.5 v operating temperature range 1 ?40c to +125c storage temperature range 1 ?65c to +150c 1 extended exposure to temperatures outside of the specified temperature range of ?40c to +85c can adversely affect the accuracy of the factory calibration. for best accuracy, store the parts within the specified operating range of ?40c to +85c. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. rate out rate in +8191 lsb ?8192 lsb 1 5 6 10 longitudinal axis clockwise rotation rate axis lateral axis 06463-004 figure 4. rate out level increase with clockwise rotation increase esd caution
adis16251 rev. a | page 7 of 7 pin configuration and fu nction descriptions dnc = do not connect 20 19 18 17 16 15 14 13 12 11 10 9 876 5 4 3 2 1 dnc com dnc dnc dio2 rst v ref com v c c v c c dnc aux dac aux adc rate filt dio1 cs din dout sclk positive output rotational direction adis16251 top view (not to scale) 06463-005 figure 5. pin configuration table 4. pin function descriptions pin no. mnemonic type 1 description 1 sclk i spi serial clock. 2 dout o spi data output. 3 din i spi data input. 4 cs i spi chip select, active low. 5, 6 dio1, dio2 i/o multifunction digital input/outputs. 7 rst i reset, active low. this resets the sensor signal conditioning circuit and initiates a start-up sequence. 8, 9, 10, 11 dnc C do not connect. 12 aux dac o auxiliary dac analog output voltage. 13 aux adc i auxiliary adc analog input voltage. 14 rate o analog rate signal output (uncalibrated). 15 filt i analog amplifier summing junction. this is used for setting the analog bandwidth. see the analog bandwidth section for more details. 16, 17 vcc s 5.0 v power supply. 18, 19 com s common. reference point for all circuitry in the adis16251. 20 vref o precision reference output. 1 s = supply; o = output; i = input. recommended layout 3.800 8 5.0865 8 0.773 16 0.500 20 1.127 20 10.173 2 7.600 4 11mm 11mm stacked lga package 06463-006 figure 6. recommended pad layout (units in millimeters)
adis16251 rev. a | page 8 of 8 typical performance characteristics 3 ?3 ?60 100 temperature (c) bias (/sec) 2 1 0 ?1 ?2 ?40 ?20 0 20 40 60 80 +1 sigma +1 sigma average 06463-007 figure 7. bias vs. temperature, adis16251 1 ?5 ?60 100 temperature (c) sensitivity (%) 0 ?1 ?2 ?3 ?4 ?40 ?20 0 20 40 60 80 +1 sigma +1 sigma average 06463-008 figure 8. sensitivity vs. temperature, adis16251 1 0.01 0.1 1000 tau (sec) root allan variance (/sec) 1 10 100 0.1 06463-009 figure 9. root allan variance vs. tau, 80/sec range 44 16 18 20 22 24 26 28 30 32 34 36 38 40 42 ?50 ?35 ?20 ?5 10 25 40 55 70 85 100 current (ma) temperature (c) fast mode normal mode 06463-012 figure 10. current vs. temperature 0 ?0.8 0 3500 time (minutes) bias (/sec) ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?0.7 500 1000 1500 2000 2500 3000 06463-011 figure 11. bias vs. time 02 rate (/sec) sensitivity (/sec/lsb) 0 0 50 100 150 0.0175 0.0177 0.0179 0.0181 0.0183 0.0185 0.0187 0.0189 06463-010 figure 12. sensitivity vs. angular rate, 80/sec range
adis16251 rev. a | page 9 of 9 3400 2000 ?60 100 temperature (c) st+ (lsb) 3200 3000 2800 2600 2400 2200 ?40 ?20 0 20 40 60 80 06463-013 figure 13. positive self-test vs. temperature ? 2000 ?3400 ?60 100 temperature (c) st? (lsb) ?2200 ?2400 ?2600 ?2800 ?3000 ?3200 ?40?200 20406080 06463-014 figure 14. negative self-test vs. temperature
adis16251 rev. a | page 10 of 10 theory of operation overview the core angular rate sensor integrated into the adis16251 is based on the analog devices i mems technology. this sensor operates on the principle of a resonator gyroscope. two polysilicon sensing structures each contain a dither frame electrostatically driven to resonance. this provides the necessary velocity ele- ment to produce a coriolis force during rotation. at two of the outer extremes of each frame (orthogonal to the dither motion) are movable fingers placed between fixed fingers to form a capaci- tive pickoff structure that senses coriolis motion. the resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. the base sensor output signal is sampled using an adc, and then the digital data is fed into a proprietary digital calibration circuit. this circuit contains calibration coefficients from the factory cali- bration, along with user-defined calibration registers that can be used to calibrate system-level errors. the calibrated gyroscope data (gyro_out) is made available through output data registers along with temperature, power supply, auxiliary adc, and relative angle output calculations. relative angle estimate the angl_out register offers the integration of the gyro_out data. in order for this information to be useful, the reference angle must be known. this can be accomplished by reading the register contents at the initial time, before starting the monitoring, or by setting its contents to zero. this number is reset to zero during power-up and is executed when the null command is used as well as after a reset command. this func- tion can be used to estimate change in an angle over a period of time. the user is cautioned to fully understand the stability requirements and the time period over which to use this estimated relative angle position. factory calibration the adis16251 provides a factory calibration that includes correction for initial tolerance and power supply variation. this calibration includes individual sensor characterization and a custom correction coefficient calculation. auxiliary adc function the auxiliary adc function integrates a standard 12-bit adc into the adis16251 to digitize other system-level analog sig- nals. the output of the adc can be monitored through the aux_adc control register, see table 5 . the adc is a 12-bit successive approximation converter. the output data is presented in straight binary format with the full-scale range extending from 0 v to 2.5 v. the 2.5 v upper limit is derived from the on-chip precision internal reference. figure 15 shows the equivalent circuit of the analog input struc- ture of the adc. the input capacitor (c1) is typically 4 pf and can be attributed to parasitic package capacitance. the two diodes provide esd protection for the analog input. care must be taken to ensure that the analog input signals never exceed the range of ?0.3 v to +3.5 v. this causes the diodes to become forward- biased and to start conducting. the diodes can handle 10 ma without causing irreversible damage. the resistor is a lumped component that represents the on resistance of the switches. the value of this resistance is typically 100 . capacitor c2 represents the adc sampling capacitor and is typically 16 pf. c2 c1 r1 v dd d d 06463-015 figure 15. equivalent analog input circuit, conversion phase: switch open, track phase: switch closed for ac applications, it is recommended to remove high fre- quency components from the analog input signal by using a low-pass filter on the analog input pin. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input must be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc. this can necessitate the use of an input buffer amplifier. when no input amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k.
adis16251 rev. a | page 11 of 11 basic operation the adis16251 is designed for simple integration into indus- trial system designs, requiring only a 5.0 v power supply and a 4-wire, industry standard serial peripheral interface (spi). all outputs and user-programmable functions are handled by a simple register structure. each register is 16 bits in length and has its own unique bit map. the 16 bits in each register consist of an upper byte (bit 8 to bit 15) and a lower byte (bit 0 to bit 7), each of which has its own 6-bit address. serial peripheral interface (spi) the adis16251 spi port includes four signals: chip select ( cs ), serial clock (sclk), data input (din), and data output (dout). the cs line enables the adis16251 spi port and frames each spi event. when this signal is high, the dout lines are in a high impedance state and the signals on din and sclk have no impact on operation. a complete data frame contains 16 clock cycles. because the spi port operates in full duplex mode, it supports simultaneous, 16-bit receive (din) and transmit (dout) functions during the same data frame. see table 2 , figure 2 , and figure 3 for detailed timing and operation of the spi port. writing to registers figure 16 displays a typical data frame for writing a command to a control register. in this case, the first bit of the din sequence is a 1, followed by a 0, the 6-bit address, and the 8-bit data com- mand. because each write command covers a single byte of data, two data frames are required when writing to the entire 16-bit space of a register. reading from registers reading the contents of a register requires a modification to the sequence in figure 16 . in this case, the first two bits in the din sequence are 0, followed by the address of the register. each register has two addresses (upper and lower), but either one can be used to access its entire 16 bits of data. the final eight bits of the din sequence are irrelevant and can be counted as dont cares during a read command. during the next data frame, the dout sequence contains the registers 16-bit data, as shown in figure 17 . although a single read command requires two separate data frames, the full duplex mode minimizes this overhead, requiring only one extra data frame when continuously sampling. cs scl k din w/r a5 a4 a3 a2 a1 a0 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 data frame write = 1 read = 0 register address data for write commands don?t care for read commands 06463-016 figure 16. din bit sequence address don?t care next command based on previous command data frame 16-bit register contents sclk din don?t care don?t care dout zero cs w /r bit data frame 06463-017 figure 17. spi sequence for read commands
adis16251 rev. a | page 12 of 12 data output register access the adis16251 provides access to calibrated rotation measure- ments, relative angle estimates, power supply measurements, temperature measurements, and an auxiliary 12-bit adc channel. this output data is continuously updating internally, regardless of user read rates. the following bit map describes the structure of all output data registers, except endurance. msb lsb nd ea d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 the msb holds the new data (nd) indicator. when the output registers are updated with new data, the nd bit goes to a 1 state. after the output data is read, it returns to a 0 state. the ea bit is used to indicate a system error or an alarm condition that can result from a number of conditions, such as a power supply that is out of the specified operating range. see the status and diagnostics section for more details. the output data is either 12 bits or 14 bits in length. for all 12-bit output data, bit d13 and bit d12 are assigned dont care status. the output data register map located in table 5 provides all the necessary details for accessing each registers data. table 6 displays the output coding for the gyro_out register. figure 18 provides an example spi read cycle for this register. table 5. data output register information name function address resolution (bits) data format scale factor (per lsb) endurance flash memory write counter 0x01, 0x00 16 binary 1 count supply_out power supply data 0x03, 0x02 12 binary 1.8315 mv gyro_out gyroscope data 0x05, 0x04 14 twos complement 0.01832/sec 1 aux_adc auxiliary analog input da ta 0x0b, 0x0a 12 binary 0.6105 mv temp_out sensor temperature data 0x 0d, 0x0c 12 twos complement 0.1453c angl_out angle output 0x0f , 0x0e 14 binary 0.03663/sec 1 assumes that the scaling is set to 80/sec. table 6. output coding example, gyro_out 1 , 2 rate of rotation binary output hex output decimal 80/sec range 40/sec range 20/sec range 150/sec 75/sec 37.5/sec 01 1111 1111 1111 0x1fff 8191 80/sec 40/sec 20/s ec 01 0001 0001 0000 0x1110 4368 20/sec 10/sec 5/s ec 00 0100 0100 0100 0x0444 1092 10/sec 5/sec 2.5/s ec 00 0010 0010 0010 0x0222 546 0.01832/sec 0.00916/sec 0.00458 /sec 00 0000 0000 0001 0x0001 1 0/sec 0/sec 0/sec 00 0000 0000 0000 0x0000 0 ?0.01832/sec ?0.00916/sec ?0.00458/sec 11 1111 1111 1111 0x3fff ?1 ?10/sec ?5/sec ?2.5/se c 11 1101 1101 1110 0x3dde ?546 ?20/sec ?10/sec ?5/sec 11 1011 1011 1100 0x3bbc ?1092 ?80/sec ?40/sec ?20/sec 10 1110 1111 0000 0x2ef0 ?4368 ?150/sec ?75/sec ?37.5 /sec 10 0000 0000 0000 0x2000 ?8192 1 two msbs have been masked off and are not considered in the coding. 2 nominal sensitivity and zero offset null performance are assumed. sclk din dout address = 000101 data = 1011 1101 1101 1110 new data, no alarm, gyro_out = ?10/sec w /r bit = 0 cs 06463-018 figure 18. example of a read cycle, 80/sec setting
adis16251 rev. a | page 13 of 13 programming and control control register overview t he adis16251 offers many programmable features controlled by writing commands to the appropriate control registers using the spi. table 7 provides a summary of these control registers, which controls the operation of the following parameters: ? calibration ? global commands ? operational control ? sample rate ? power management ? digital filtering ? dynamic range ? dac output ? digital i/o ? operational status and diagnostics ? self test ? status conditions ? alarms control register structure the adis16251 uses a temporary, ram-based memory structure to facilitate the control registers displayed in table 7 . the start-up configuration is stored in a flash memory structure that automatically loads into the control registers during the start-up sequence. each nonvolatile register has a correspond- ing flash memory location for storing the latest configuration contents. because flash memory has endurance limitations, the contents of each nonvolatile register must be stored to flash manually. please note that the contents of the control register are only nonvolatile when they are stored to flash. the manual flash update command, made available in the command register, provides this function. the endurance register provides a counter, which allows for reliability management against the flash memorys write cycle specification. table 7. control register mapping register name type volatility address bytes function reference table gyro_off r/w nonvolatile 0x15, 0x14 2 gyroscope bias offset factor table 8 , table 9 gyro_scale r/w nonvol atile 0x17, 0x16 2 gyroscope scale factor table 10 , table 11 0x18 to 0x1f 8 reserved alm_mag1 r/w nonvolatile 0x21, 0x20 2 al arm 1 amplitude threshold and polarity table 30 , table 31 alm_mag2 r/w nonvolatile 0x23, 0x22 2 al arm 2 amplitude threshold and polarity table 34 , table 35 alm_smpl1 r/w nonvolat ile 0x25, 0x24 2 alarm 1 sample period table 32 , table 33 alm_smpl2 r/w nonvolat ile 0x27, 0x26 2 alarm 2 sample period table 36 , table 37 alm_ctrl r/w nonvolatile 0x29, 0x28 2 alarm control register table 38 , table 39 0x2a to 0x2f 6 reserved aux_dac r/w volatile 0x31, 0x30 2 auxiliary dac data table 20 , table 21 gpio_ctrl r/w volatile 0x33, 0x32 2 auxiliary digital i/o control register table 22 , table 23 msc_ctrl r/w nonvolatile 1 0x35, 0x34 2 miscellaneous control register table 25 , table 26 smpl_prd r/w nonvolatile 0x37, 0x 36 2 adc sample period control table 14 , table 15 sens/avg r/w nonvolatile 0x39, 0x38 2 defines the dynamic range (sensitivity setting) and the number of taps for the digital filter table 18 , table 19 slp_cnt r/w volatile 0x3b, 0x3a 2 counter used to determine length of power- down mode table 16 , table 17 status r volatile 0x3d, 0x3c 2 system status register table 27 , table 28 command w n/a 0x3f, 0x3e 2 system command register table 12 , table 13 1 the contents of the upper byte are nonvolatile; the contents of the lower byte are volatile.
adis16251 rev. a | page 14 of 14 calibration the adis16251 is factory-calibrated for sensitivity and bias. it also provides several user calibration functions for simplifying field-level corrections. the calibration factors are stored in nonvolatile memory and are applied using the following linear calibration equation: y = mx + b where: y is the calibrated output data. m is the sensitivity scale factor. x is the precalibration data. b is the offset scale factor. th ere are three options for system-level calibrations of the bias in the adis16251: autonull, factory calibration restore, and manual calibration updates. the autonull and factory reset options are described in the global commands section. optional field-level calibrations use the preceding equation and require the following two steps: 1. characterize the behavior of the adis16251 at predefined critical operating conditions. 2. use this characterization data to calculate and load the contents of gyro_off (b) and gyro_scale (m). the gyro_off provides a calibration range of 75/sec, and its contents are nonvolatile. the gyro_scale register provides a calibration range of 0 to 1.9995, and its contents are also nonvolatile. table 8. gyro_off register definition address scale 1 default format access 0x15, 0x14 0.00458/sec 0x0000 twos complement r/w 1 scale is the weight of each lsb. table 9. gyro_off bit descriptions bit description 15:14 not used 13:0 data bits table 10. gyro_scale register definition address scale 1 default 2 format access 0x17, 0x16 0.0487% 0x0800 binary r/w 1 scale is the weight of each lsb. 2 equates to a scale factor of one. table 11. gyro_scale bit descriptions bit description 15:12 not used 11:0 data bits global commands the adis16251 provides global commands for common opera- tions such as autonull, factory calibration restore, manual flash update, auxiliary dac latch, and software reset. each of these global commands has a unique control bit assigned to it in the command register and is initiated by writing a 1 to its assigned bit. th e autonull function does two things: it resets the contents of the angl_out register to zero, and it adjusts the gyro_out register to zero. this automated adjustment requires the follow- ing two steps: 1. read gyro_out. 2. write the opposite of this value into the gyro_off register. sensor noise influences the accuracy of this step. for optimal calibration accuracy, set the number of filtering taps to its maximum, wait for the appropriate number of samples to process through the filter, and then exercise this option. the factory calibration restore command sets the contents of gyro_off to 0x0000 and gyro_scale to 0x0800, erasing any field-level calibration contents. the manual flash update writes the contents of each nonvolatile register into flash mem- ory for storage. this process takes approximately 50 ms and requires the power supply voltage to be within specification for the duration of the event. it is worth noting that this operation also automatically follows the autonull and factory reset commands. the dac latch command loads the contents of aux_dac into the dac latches. since the aux_dac contents must be updated one byte at a time, this command ensures a stable dac output voltage during updates. finally, the software reset command sends the adis16251 digital processor into a restart sequence, effectively doing the same thing as the rst line. table 12. command register definition address default format access 0x3f, 0x3e n/a n/a write only table 13. command bit descriptions bit description 15:8 not used 7 software reset command 6:4 not used 3 manual flash update command 2 auxiliary dac data latch 1 factory calibration restore command 0 autonull command
adis16251 rev. a | page 15 of 15 operational control internal sample rate the internal sample rate defines how often data output variables are updated, independent of the rate at which they are read out on the spi port. the smpl_prd register controls the adis16251s internal sample rate and has two parts: a selectable time base and a multiplier. the sample period can be calculated using the following equation: t s = t b ( n s + 1) where: t s is the sample period. t b is the time base. n s is the increment setting. the default value is the maximum 256 sps, and the contents of this register are nonvolatile. table 14. smpl_prd register definition address default format access 0x37, 0x36 0x0001 n/a r/w table 15. smpl_prd bit descriptions bit description 15:8 not used 7 time base, 0 = 1.953 ms, 1 = 60.54 ms 6:0 multiplier the following is an example calculation of the sample period for the adis16251: if smpl_prd = 0x0007, b7 b0 = 00000111 b7 = 0 t b = 1.953 ms b6 b0 = 000000111 n s = 7 t s = t b (n s + 1) = 1.953 ms (7 + 1) = 15.624 ms f s = 1M t s = 64 sps the sample rate setting has a direct impact on the spi data rate capability. for sample rates of 64 sps and above, the spi sclk can run at a rate up to 2.5 mhz. for sample rates below 64 sps, the spi sclk can run at a rate up to 1 mhz. the sample rate setting also affects the power dissipation. when the sample rate is set below 64 sps, the power dissipation reduces by a factor of 60%. the two different modes of operation offer a system-level trade-off between performance (sample rate, serial transfer rate) and power dissipation. power management in addition to offering two different performance modes for power optimization, the adis16251 offers a programmable shutdown period. writing the appropriate sleep time to the slp_cnt register shuts the device down for the specified time. the following example provides an illustration of this relationship: b7 b0 = 00000110 sleep period = 3 sec after completing the sleep period, the adis16251 returns to normal operation. if the measurements are required before the sleep period completion, the adis16251 can be awakened by putting the cs line in a zero logic state. otherwise, the cs line must be kept high to maintain sleep mode. table 16. slp_cnt register definition address scale 1 default format access 0x3b, 0x3a 0.5 sec 0x0000 binary r/w 1 scale is the weight of each lsb. table 17. slp_cnt bit descriptions bit description 15:8 not used 7:0 data bits analog bandwidth the analog bandwidth of the adis16251 is 49 hz. this band- width can be reduced by placing an external capacitor across the rate and filt pins. in this case, the analog bandwidth can be calculated using the following equation: f out = 1/(2 r out ( c out + 0.018 f)) where: r out = 180 k. c out = external capacitance. digital filtering the adis16251 gyro_out signal path has a nominal analog bandwidth of 49 hz. the adis16251 provides a bartlett window fir filter for additional noise reduction on all of the output data registers. the sens/avg register stores the number of taps in this filter in seven power-of-two, step sizes (that is, 2 m = 1, 2, 4, 16, 32, 64, and 128). filter setup requires one simple step: write the appropriate m factor to the assigned bits in the sens/avg register. the bit assignments are listed in table 19 . the fol- lowing equation offers a frequency response relationship for this filter: ) sin( ) sin( )()()( 2 s s a a b tf n tfn fhfhfh =?=
adis16251 rev. a | page 16 of 16 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0.001 0.01 0.1 1 magnitude (db) frequency (f/fs) n = 128 n = 16 n = 2 n = 4 06463-019 figure 19. bartlett window fir frequency response dynamic range the adis16251 provides three dynamic range settings: 20/sec, 40/sec, and 80/sec. the lower dynamic range settings (20/sec, 40/sec) limit the minimum filter tap sizes in order to maintain the resolution as the maximum rate measurements decrease. the recommended order for pro- gramming the sens/avg register is (1) dynamic range and (2) filtering response. the contents of the sens/avg register are nonvolatile. table 18. sens/avg register definition address default format access 0x39, 0x38 0x0402 binary r/w table 19. sens/avg bit descriptions bit value description 15:11 not used 10:8 sensitivity selection bits 100 80/sec (default condition) 010 40/sec, filter taps 4 (bits [3:0] 0x02) 001 20/sec, filter taps 16 (bits [3:0] 0x04) 7:4 not used 3:0 filter tap setting, m = binary number (number of taps, n = 2 m ) auxiliary dac the auxiliary dac provides a 12-bit level adjustment function. the aux_dac register controls the operation of this feature. it offers a rail-to-rail buffered output that has a range of 0 v to 2.5 v. the dac can drive its output to within 5 mv of the ground ref- erence when it is not a sinking current. as the output approaches ground, the linearity begins to degrade (100 lsb beginning point). as the sink current increases, the nonlinear range increases. the dac output latch function, contained in the command register, provides continuous operation while writing each byte of this register. the contents of this register are volatile, which means that the desired output level must be set after every reset and power cycle event. table 20. aux_dac register definition address default format access 0x31, 0x30 0x0000 binary r/w table 21. aux_dac bit descriptions bit description 15:12 not used 11:0 data bits general-purpose i/o the adis16251 provides two general-purpose pins that enable digital i/o control using the spi. the gpio_ctrl control register establishes the configuration of these pins and handles the spi- to-pin controls. each pin provides the flexibility of both input (read) and output (write) operations. for example, writing a 0x0202 to this register establishes line 2 as an output and sets its level as a 1. writing 0x0000 to this register establishes both lines as inputs, and their status can be read through bit 0 and bit 1 of this register. t he digital i/o lines are also available for data-ready and alarm/ error indications. in the event of conflict, the following priority structure governs the digital i/o configuration: ? msc_ctrl ? alm_ctrl ? gpio_ctrl table 22. gpio_ctrl register definition address default format access 0x33, 0x32 0x0000 n/a r/w table 23. gpio_ctrl bit descriptions bit description 15:10 not used 9 general-purpose i/o line 2 polarity 1 = high 0 = low 8 general-purpose i/o line 1 polarity 1 = high 0 = low 7:2 not used 1 general-purpose i/o line 2, data direction control 1 = output 0 = input 0 general-purpose i/o line 1, data direction control 1 = output 0 = input
adis16251 rev. a | page 17 of 17 status and diagnostics the adis16251 provides a number of status and diagnostic functions. table 24 provides a summary of these functions, along with their appropriate control registers. table 24. status and diagnostic functions function register data-ready i/o indicator msc_ctrl self-test, mechanical check for mems sensor msc_ctrl status, check for predefined error conditions status flash memory endurance endurance alarms, configure and check for user- specific conditions alm_mag1/alm_mag2 alm_smpl1/alm_smpl2 alm_ctrl data-ready i/o indicator the data-ready function provides an indication of updated out- put data. the msc_ctrl register provides the opportunity to configure either of the general-purpose i/o pins (dio1 and dio2) as a data-ready indicator signal. after each output register update, the digital i/o changes states, and then returns to its original state, creating a pulsed waveform. the duty cycle of that waveform is between 15% and 35%. table 25. msc_ctrl register definition address default format access 0x35, 0x34 0x0000 n/a r/w table 26. msc_ctrl bit descriptions bit description 15:11 not used 10 internal self-test enable 1 = enabled 0 = disabled 9 external negative rota tion self-test enable 1 = enabled 0 = disabled 8 external positive rotation self-test enable 1 = enabled 0 = disabled 7:3 not used 2 data-ready enable 1 = enabled 0 = disabled 1 data-ready polarity 1 = active high 0 = active low 0 data-ready line select 1 = dio2 0 = dio1 self-test the msc_ctrl register also provides a self-test function, which verifies the mems sensors mechanical integrity. there are two different self-test options: (1) internal self-test and (2) external self-test. the internal test provides a simple, two- step process for checking the mems sensor: (1) start the process by writing a 1 to bit 10 in the msc_ctrl register and (2) check the result by reading bit 5 of the status register, after 35 ms. the external self-test is a static condition that can be enabled and disabled. in this test, both positive and negative mems sensor movements are available. after writing to the appropriate control bit, the gyro_out register reflects the changes after a delay that reflects the sensor signal chain response time. for example, the standard 49 hz bandwidth reflects an exponential response with a time constant of 3.2 ms. if the bandwidth is reduced externally (a capacitor across rate and filt pins) or internally (increasing the number of filter taps, see sens/avg register), this time constant increases. for the internal self-test option, increasing the delay can produce false alarms, since the internal timing for this function is optimized for maximum bandwidth. the appropriate bit definitions for self-test are listed in tabl e 25 and table 26 . status conditions the status register contains the following error-condition flags: alarm conditions, self-test status, angular rate over range, spi communication failure, control register update failure, and power supply out of range. see table 27 and table 28 for the appropriate register access and bit assignment for each flag. the bits assigned for checking the power supply range and the angular rate overrange automatically reset to zero when the error condition no longer exists. the remaining error-flag bits in the status register require a read in order to return them to zero. note that a status register read clears all of the bits to zero. table 27. status register definition address default format access 0x3d, 0x3c 0x0000 n/a read-only
adis16251 rev. a | page 18 of 18 table 28. status bit descriptions bit description 15:10 not used 9 alarm 2 status 1 = active 0 = inactive 8 alarm 1 status 1 = active 0 = inactive 7:6 not used 5 self-test diagnostic error flag 1 = error condition 0 = normal operation 4 angular rate over range 1 = error condition 0 = normal operation 3 spi communications failure 1 = error condition 0 = normal operation 2 control register update failed 1 = error condition 0 = normal operation 1 power supply above 5.25 v 1 = above 5.25 v 0 = below 5.25 v (normal) 0 power supply below 4.75 v 1 = below 4.75 v 0 = above 4.75 v (normal) flash memory endurance the endurance register maintains a running count of writes to the flash memory. it provides up to 32,768 counts. note that if this count is exceeded, the register wraps around, and goes back to zero, before beginning to increment again. table 29. endurance register definition address default format access 0x01, 0x00 n/a binary read-only alarms t he adis16251 provides two independent alarm options for event detection. event detections occur when output register data meets the configured conditions. configuration options are: ? all output data registers are available for monitoring as the source data. ? the source data can be filtered or unfiltered. ? comparisons can be static or dynamic (rate of change). ? the threshold levels and times are configurable. ? comparison can be greater than or less than. the alm_mag1 register and the alm_mag2 register both establish the threshold level for detecting events. they take on the format of the source data and provide a bit for establishing the greater than/less than comparison direction. when making dynamic comparisons, the alm_smpl1 register and the alm_smpl2 register establish the number of averages taken for the source data as a reference for comparison. in this configuration, each subsequent source data sample is subtracted from the previous one, establishing an instantaneous delta. the rate of change calculation is ?oris )()1( 1 1 c c n n ds c my alarm changeofrate nyny n y ds <>? ?+ = = where: n ds is the number of samples in alm_smpl1/alm_smpl2. y(n) is the sampled output data. m c is the magnitude for comparison in alm_mag1/ alm_mag2. y c is the factor to be compared with m c . > or < is determined by the msb in alm_mag1/alm_mag2. the alm_ctrl register controls the source data selection, static/ dynamic selection, filtering selection, and digital i/o usage for the alarms. table 30. alm_mag1 register definition address default format access 0x21, 0x20 0x0000 n/a r/w table 31. alm_mag1 bit descriptions bit description 15 comparison polarity: 1 = greater than, 0 = less than 14 not used 13:0 data bits: format matches source data format table 32. alm_smpl1 register definition address default format access 0x25, 0x24 0x0000 binary r/w table 33. alm_smpl1 bit descriptions bit description 15:8 not used 7:0 data bits table 34. alm_mag2 register definition address default format access 0x23, 0x22 0x0000 n/a r/w table 35. alm_mag2 bit descriptions bit description 15 comparison polarity 1 = greater than 0 = less than 14 not used 13:0 data bits: format matches source data format
adis16251 rev. a | page 19 of 19 table 36. alm_smpl2 register definition address default format access 0x27, 0x26 0x0000 binary r/w table 37. alm_smpl2 bit descriptions bit description 15:8 not used 7:0 data bits table 38. alm_ctrl register definition address default format access 0x29, 0x28 0x0000 n/a r/w table 39. alm_ctrl bit descriptions bit value description 15 rate of change (roc) enable for alarm 2 1 = rate of change 0 = static level 14:12 alarm 2 source selection 000 disable 001 power supply output 010 gyroscope output 011 inactive 100 inactive 101 auxiliary adc output 110 temperature sensor output 111 inactive 11 rate of change (roc) enable for alarm 1 1 = rate of change 0 = static level 10:8 alarm 1 source selection, same coding as alarm 2, bits [14:12] 7:5 not used 4 filtered data comparison 1 = filtered data 0 = unfiltered data 3 not used 2 alarm output enable 1 = enabled 0 = disabled 1 alarm output polarity 1 = active high 0 = active low 0 alarm output line select 1 = dio2 0 = dio1
adis16251 rev. a | page 20 of 20 second-level assembly the adis16251 can be attached to the second-level assembly board using sn63 (or equivalent) or a pb-free solder. figure 20 and table 40 provide acceptable solder reflow profiles for each solder type. please note that these profiles may not be the opti- mum profile for the users application. in no case should 260c be exceeded. it is recommended that the user develop a reflow profile based upon the specific application. in general, the lowest peak temperature and shortest dwell time above the melt temperature of the solder result in less shock and less stress to the product. in addition, evaluating the cooling rate and peak temperature can result in a more reliable assembly. 06463-020 t p t l t 25c to peak t s preheat critical zone t l to t p temperature time ramp-down ramp-up t smin t smax t p t l figure 20. acceptable solder reflow profiles table 40. acceptable solder reflow profiles 1 profile feature conditions sn63/pb37 pb-free average ramp rate (t l to t p ) 3c/sec max 3c/sec max preheat minimum temperature (t smin ) 100c 150c maximum temperature (t smax ) 150c 200c time (between t smin to t smax ) (t s ) 60 sec to 120 sec 60 sec to 180 sec t smax to t l ramp-up rate 3c/sec 3c/sec time maintained above liquidous temperature (t l ) liquidous temperature (t l ) 183c 217c time (t l ) 60 sec to 150 sec 60 sec to 150 sec peak temperature (t p ) 240c + 0c/C5c 260c + 0c/C5c time within 5c of actual t p 10 sec to 30 sec 20 sec to 40 sec ramp-down rate 6c/sec max 6c/sec max time 25c to t p 6 min max 8 min max 1 per ipc/jedec j-std-020c.
adis16251 rev. a | page 21 of 21 outline dimensions 022007-b side view top view bottom view pin 1 indicator 1.000 bsc (20 ) 5.50 max 11.00 typ 1 5 6 10 11 15 16 20 11.15 max 7.600 bsc (4 ) 3.800 bsc (8 ) 7.00 typ 10.173 bsc (2 ) 0.200 min (all sides ) 0.900 bsc (16 ) 0.373 bsc (20 ) figure 21. 20-terminal stacked land grid array [lga] (cc-20-1) dimensions shown in millimeters ordering guide model temperature range packag e description package option ADIS16251ACCZ 1 ?40c to +85c 20-terminal stacked land grid array [lga] cc-20-1 adis16251/pcbz 1 evaluation board 1 z = rohs compliant part.
adis16251 rev. a | page 22 of 22 notes
adis16251 rev. a | page 23 of 23 notes
adis16251 rev. a | page 24 of 24 notes ?2007C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06463-0-11/09(a)

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